About me

My name is Hunter Coffman and I am a part of Apple’s design verification team. I am an alumni from the University of California, Santa Cruz where I obtained my Master’s of Science in Computer Engineering in September 2020. I also obtained my Bachelor’s of Science in Computer Science, Minor in Computer Engineering from the same institution in June 2019.

Academics

My particular research interests lie in the domain of computer architecture, improving hardware design flows, and emerging hardware description languages (HDLs) such as Chisel and Pyrope. I’m an alumni of the MASC (Micro-Architecture Santa Cruz) research group. While I was a member, our main focus was on making our own HDL called Pyrope and also making the hardware design flow much more efficient through our project LiveHD. My specific contribution to LiveHD is currently through creating a bitwidth inference/optimization pass and also a Chisel/FIRRTL interface with the framework. More on my contributions can be found in my thesis.

Work Experience

Here is a summary of my work experience. For a more detailed history, go to the Resume page found at the top of this site.

From June 2019 to September 2019 I worked as an intern for SiFive’s Verification Engineering team, specifically focusing on Core Verification. I added new test infrastructure using the Verilog DPI interface to make calls out to C functions that controled signals internal to the core. I also worked on verifying the core’s interaction with a newly designed memory protection component for a very large customer. There I gained experience in verification methodology, writing Chisel code, applying academic concepts to real-life solutions (cache coherency protocols), and working in a high-intensity (but also high fun!) work environment.

For those who may not know, SiFive is a company that was made in making RISC-V CoreIP. A lot of the original designers of RISC-V work for the company. Go SiFive!

Since September 2020, I’ve been a member of Apple’s design verification team. Here, I’ve been working on verifying block-level components of our designs using UVM.