Resume

If you would like to see this resume in a .pdf format: click here!

Education

University of California, Santa Cruz

• M.S. in Computer Engineering (September 2020, GPA: 4.0)
• B.S. in Computer Science, Minor in Computer Engineering (June 2019)

Work experience

SOC Design Verification Engineer

Apple — September 2020 to Present

• (More specific details about my work in this role will be added in the future.)

Undergraduate & Graduate Researcher (MASC Lab)

University of California, Santa Cruz — May 2018 to September 2020

• Served as one of the main contributors to the lab’s open-source hardware compiler, LiveHD.
  • Worked on a novel thesis that focused on bi-directionally translating multiple HDLs between one another to create a language-agnostic framework. (See the Notable Projects section below)
  • Implemented an algorithm which minimizes bitwidths of variables in hardware designs.

Microprocessor Verification Engineer, Intern

SiFive — June 2019 to September 2019

• Verified the interaction between our cores and a new memory protection unit.
• Designed new verification infrastructure that leveraged the Verilog DPI interface to have C functions control signals internal to the core during simulation.

Teaching Assistant: Microprocessor System Design, Computer Architecture

Jack Baskin School of Engineering, UCSC — September 2019 to March 2020

• Acted as a mentor for undergraduates, teaching them the fundamentals of microprocessor design leveraging C, hardware components, and inter-device communication.
• Taught students about computer architecture principles and pipelining techniques.

Skills

Programming Languages:

• Proficient: Verilog, C++, C
• Familiar: Chisel, Haskell, Python, Java

Frameworks and Tools:

• RISC-V, UVM, Verdi, AHB, APB, AXI, TileLink, Yosys Open Synthesis Suite, Verilator Simulation Tool, Git, Unix, LaTeX

Notable Projects

Thesis: Bridging Intermediate Representations to Achieve Hardware Design Language Translation

• Designed and implemented novel translation techniques which bi-directionally map the FIRRTL intermediate representation (IR) to the LNAST IR. Used in the open-source hardware design framework, LiveHD.
• Created a process that translates from LiveHD’s internal graph-like representation for a hardware design to its abstract syntax tree-like representation. This facilitated the translation between low-level HDLs like Verilog to abstract, open-source HDLs like Chisel or Pyrope.
• At the time of writing, this work performed at speeds between four to ten times faster than any other similar works.

RISC-V Processor

• Created an in-order five stage process in Verilog. It executes any instructions in the 32I/64I set. Used dhrystone as a testbench.
• After completion, used Yosys synthesis tool to optimize design.